#
# Copyright (C) 2024, Advanced Micro Devices, Inc. All rights reserved.
# SPDX-License-Identifier: X11
#

# Retrieve the cache repository directory from the argument
set CACHE_REPO_DIR [lindex $argv 0]  ;# Get the first argument from the command line

#Create the project in the output directory
create_project vivado_prj_from_tcl -force  -part xcvc1902-vsva2197-2MP-e-S

#Set the board part
set_property board_part xilinx.com:vck190:part0:3.2 [current_project]

config_ip_cache -use_cache_location ../$CACHE_REPO_DIR/   

#####Read all sources for building the project#####

#Generate the system BD that has only CIPS and DDR NOCs
source ../../sources/bd/bd.tcl

#Read the RTL files that has XPM NMUs and NSUs instantiated along with traffic generators and BRAM 
add_files ../../sources/rtl

#Generate the XCI files for BRAMs, Performance Traffic Generators and VIO IPs
source ../../sources/ip/axi_bram_ctrl_pl_slave_from_pl_master.tcl
source ../../sources/ip/axi_bram_ctrl_pl_slave_from_ps.tcl
source ../../sources/ip/axis_vio_pl_master_to_ddr.tcl
source ../../sources/ip/axis_vio_pl_master_to_pl_slave.tcl
source ../../sources/ip/axis_vio_pl_master_to_ps.tcl
source ../../sources/ip/axis_MxN_vio.tcl
source ../../sources/ip/axi_tg_pl_to_pl.tcl
source ../../sources/ip/axi_tg_pl_to_ps.tcl
source ../../sources/ip/axi_tg_pl_master_to_ddr.tcl


#Read the XDC files for creating NoC connection, setting its QoS settings and the aperture of XPM NSUs. 
add_files -fileset constrs_1 ../../sources/xdc/noc_constraints.xdc

#Read the XDC files that has constraints for creating ILAs and for connecting them to debug hub in the design. This constraint is auto-generated by the tool based on "Set up Debug" flow.
add_files -fileset constrs_1 ../../sources/xdc/design_1_wrapper_debug.xdc

#####Set the USED_IN {synthesis_pre} for NoC constraints#####
set_property USED_IN {synthesis_pre} [get_files noc_constraints.xdc]

#####Generate all targets : XCI/BD######
generate_target {synthesis instantiation_template} [get_files { axis_MxN_vio.xci axi_bram_ctrl_pl_slave_from_pl_master.xci axi_bram_ctrl_pl_slave_from_ps.xci axis_vio_pl_master_to_ddr.xci axis_vio_pl_master_to_pl_slave.xci axis_vio_pl_master_to_ps.xci axi_tg_pl_master_to_ddr.xci axi_tg_pl_to_pl.xci axi_tg_pl_to_ps.xci design_1.bd}]

##Updating the sourcefile set 
update_compile_order -fileset sources_1

##### Validate the NoC to see the project level NoC endpoints and paths
#validate_noc

##Launch Synthesis
#start_gui
launch_runs synth_1 -jobs 4
wait_on_run synth_1 
#exit
